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general description the max4810/max4811/max4812 integrated circuits generate high-voltage, high-frequency, unipolar or bipo- lar pulses from low-voltage logic inputs. these dual pulsers feature independent logic inputs, independent high-voltage pulser outputs with active clamps and independent high-voltage supply inputs. the max4810/max4811/max4812 feature a 9 output impedance for the high-voltage outputs, and a 27 impedance for the active clamp. the high-voltage out- puts are guaranteed to provide 1.3a output current. all devices use three logic inputs per channel to control the positive and negative pulses and active clamp. also included are two independent enable inputs. disabling en ensures the output mosfets are not accidentally turned on during fast power-supply ramping. this allows for faster ramp times and smaller delays between puls- ing modes. a low-power shutdown mode reduces power consumption to less than 1?. all digital inputs are cmos compatible. the max4810 includes clamp output overvoltage pro- tection, while the max4811 features both pulser output and clamp output overvoltage protection. the max4812 does not provide overvoltage protection. see the ordering information/selector guide . the max4810/max4811/max4812 are available in a 56-pin (7mm x 7mm), tqfn exposed-pad package and are specified over the 0? to +70? commercial tem- perature range. features ? highly integrated, high-voltage, high-frequency unipolar/bipolar pulser ? 9 output impedance and 1.3a (min) output current ? 27 active clamp ? pulser and clamp overvoltage protection (max4810/max4811) ? 0 to +220v unipolar or ?10v bipolar outputs ? matched rise/fall times and matched propagation delays ? cmos-compatible logic inputs ? 56-pin, 7mm x 7mm, tqfn package max4810/max4811/max4812 dual, unipolar/bipolar, high-voltage digital pulsers ________________________________________________________________ maxim integrated products 1 19-4138; rev 0; 10/08 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available pin configuration top view max4810 max4811 max4812 tqfn 7mm x 7mm 15 17 16 18 19 20 21 22 23 24 25 26 27 28 gnd v cc1 inn1 inc1 inp1 en1 agnd en2 inp2 inc2 inn2 v cc2 gnd c dp1 gnd v cc1 c gc1 c dc1 v ee1 v ss v dd v ee2 c dc2 c gc2 v cc2 gnd c dp2 48 47 46 45 44 43 54 53 56 55 52 51 50 49 1 2 3 4 5 6 7 8 9 1011121314 42 41 40 39 38 37 36 35 34 33 32 31 30 29 v nn1 c gn1 c dn1 v nn1 n.c. on1 ocn1 gnd ocp1 op1 n.c. v pp1 v pp1 c gp1 v nn2 c gn2 c dn2 v nn2 n.c. on2 ocn2 gnd ocp2 op2 n.c. v pp2 v pp2 c gp2 *ep = exposed pad, connect ep to v ss . *ep + shdn ordering information/ selector guide note: all devices are specified over the 0? to +70? operating temperature range. + denotes a lead-free/rohs-compliant package. * future productcontact factory for availability. ** ep = exposed pad. part protected outputs output current (a) pin- package max4810 ctn+ ocp_, ocn_ 1.3 56 tqfn-ep** max4811 ctn+ ocp_, ocn_, op_, on_ 1.3 56 tqfn-ep** max4812 ctn+* none 1.3 56 tqfn-ep** warning: the max4810/max4811/max4812 are designed to operate with high voltages. exercise caution. ultrasound medical imaging cleaning equipment flaw detection piezoelectric drivers test instruments applications
max4810/max4811/max4812 dual, unipolar/bipolar, high-voltage digital pulsers 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v dd = +2.7v to +6v, v cc_ = +4.75v to +12.6v, v ee_ = -12.6v to -4.75v, v nn_ = -200v to 0, v pp_ = 0 to (v nn_ + 200v), v ss the lower of v nn1 or v nn2 , t a = t j = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 3) (see figures 8, 9, and 10.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. (voltages referenced to gnd.) v dd logic supply voltage........................................-0.3v to +6v v cc_ output driver positive supply voltage ..........-0.3v to +15v v ee_ output driver negative supply voltage.........-15v to +0.3v v pp_ high positive supply voltage.......................-0.3v to +230v v nn_ high negative supply voltage ....................-230v to +0.3v v ss voltage ................................................(v pp_ - 250v) to v nn_ v pp1 - v nn1 , v pp2 - v nn2 supply voltage............-0.6v to +250v inp_, inn_, inc_, en_, shdn logic input...-0.3v to v dd + 0.3v o p_, o cp_ , o ln_ , o n_ ..............(-0.3v + v nn_ ) to (-0.3v to v pp_ ) c gn_ voltage............................(-0.3v + v nn_ ) to (+15v + v nn_ ) c gp_ voltage .............................(+0.3v + v pp_ ) to (-15v + v pp_ ) c gc_ voltage...........................................................-15v to +15v c dc_, c dp_ , c dn_ voltage......................................-0.3v to v cc_ peak current per output channel ........................................3.0a continuous power dissipation (t a = +70?) (note 1) 56-pin tqfn (derate 40mw/? above +70?) ..........3200mw thermal resistance (note 2) ja ................................................................................25?/w jc ...............................................................................0.8?/w operating temperature range...............................0? to +70? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units power supply (v dd , v cc_ , v ee _, v pp_ , v nn_ ) logic supply voltage v dd +2.7 +3 +6 v positive drive supply voltage v cc_ +4.75 +12 +12.6 v negative drive supply voltage v ee_ -12.6 -12 -4.75 v high-side supply voltage v pp_ 0 v nn_ + 220 v low-side supply voltage v nn_ -200 0v v pp_ - v nn_ supply voltage 0 +220 v supply current (single channel) v inn_ /v inp_ = 0 , v shdn = 0 1 v dd supply current i dd v en_ = v dd , v shdn = v dd , v inc_ = 0 or v dd , v inn_ = v inp_ , f = 5mhz 100 200 ? v shdn = 0, ch1 and ch2 1 v en_ = v dd , v shdn = v dd, ch1 and ch2 130 200 ? v en_ = v dd , v shdn = v dd , v inc_ = 0 or v dd , v inn_ = v inp_ , f = 5mhz, v cc_ = 5v, v dd = 3v, only one channel switching 15 v cc_ supply current i cc_ v en_ = v dd , v shdn = v dd , v inc_ = 0 or v dd , v inn_ = v inp_ , f = 5mhz, v cc_ = 12v, v dd = 3v, only one channel switching 36 ma note 1: this specification is based on the thermal characteristic of the package, the maximum junction temperature, and the setup described by jedec 51. the maximum power dissipation for the max4810/max4811/max4812 might be limited by the thermal protection included in the device. note 2: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four- layer board. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial .
max4810/max4811/max4812 dual, unipolar/bipolar, high-voltage digital pulsers _______________________________________________________________________________________ 3 electrical characteristics (continued) (v dd = +2.7v to +6v, v cc_ = +4.75v to +12.6v, v ee_ = -12.6v to -4.75v, v nn_ = -200v to 0, v pp_ = 0 to (v nn_ + 200v), v ss the lower of v nn1 or v nn2 , t a = t j = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 3) (see figures 8, 9, and 10.) parameter symbol conditions min typ max units v shdn = 0, ch1 and ch2 25 v en_ = v dd , v shdn = v dd , ch1 and ch2 1 v en_ = v dd , v shdn = v dd , v inc_ = 0 or v dd , v inn_ = v inp_ , f = 5mhz, v ee_ = -5v, only one channel switching 200 v ee_ supply current i ee_ v en_ = v dd , v shdn = v dd , v inc_ = 0 or v dd , v inn_ = v inp_ , f = 5mhz, v ee_ = -12v, only one channel switching 200 ? v shdn = 0, ch1 and ch2 1 v en_ = v dd , v shdn = v dd , ch1 and ch2 90 160 ? v e n _ = v d d , v shdn = v d d , v i n c _ = 0 or v d d , v i n n _ = v i np_ , f = 5m h z, v p p _ = + 5v , v n n _ = - 5v , no l oad , onl y one channel sw i tchi ng 9 v pp_ supply current i pp_ v en_ = v dd , v shdn = v dd , v inc_ = 0 or v dd , v pp_ = +80v, v nn_ = -80v, pulse repetition frequency = 10khz, f = 10mhz, 4 periods, no load, only one channel switching 0.6 ma v shdn = 0, ch1 and ch2 1 v en_ = v dd , v shdn = v dd , ch1 and ch2 40 80 ? v e n _ = v d d , v shdn = v d d , v i n c _ = 0 or v d d , v i n n _ = v i np_ , f = 5m h z, v n n _ = - 5v , v p p _ = + 5v , no l oad , onl y one channel sw i tchi ng 9 v nn_ supply current i nn_ v en_ = v dd , v shdn = v dd , v inc_ = 0 or v dd , v pp_ = +80v, v nn_ = -80v, pulse repetition frequency = 10khz, f = 10mhz, 4 periods, no load, only one channel switching 0.6 ma logic inputs (en_, shdn , inn_, inp_, inc_) low-level input voltage v il 0.25 x v dd v high-level input voltage v ih 0.75 x v dd v logic-input capacitance c in 5pf logic-input leakage i in v in = 0 or v dd ? ? output (out_) no load at out_ v nn_ v pp_ unprotected outputs (see the ordering information/selector guide ), 100ma load v nn_ + 1.5 v pp_ - 1.5 out_ output-voltage range v out_ protected outputs (see the ordering information/selector guide ), 100ma load v nn_ + 2.5 v pp_ - 2.5 v i op _ = - 100m a, v c c _ = + 12v ? 5%, d c - coup l ed 9 17 low-side small-signal output impedance r ols i op _ = - 100m a, v c c _ = + 5v ? 5%, d c - coup l ed 9.5 18
max4810/max4811/max4812 dual, unipolar/bipolar, high-voltage digital pulsers 4 _______________________________________________________________________________________ electrical characteristics (continued) (v dd = +2.7v to +6v, v cc_ = +4.75v to +12.6v, v ee_ = -12.6v to -4.75v, v nn_ = -200v to 0, v pp_ = 0 to (v nn_ + 200v), v ss the lower of v nn1 or v nn2 , t a = t j = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 3) (see figures 8, 9, and 10.) parameter symbol conditions min typ max units i op _ = - 100m a, v c c _ = + 12v ? 5%, d c - coup l ed 10.5 17 high-side small-signal output impedance r ohs i op _ = - 100m a, v c c _ = + 5v ? 5%, d c - coup l ed 12 18 low-side output current i ol v cc_ = +12v ?%, v out_ - v nn_ = 100v 1.3 a high-side output current i oh v cc_ = +12v ?%, v out_ - v pp_ = 100v 1.3 a max4810 45 off-output capacitance c o ( off ) op_, on_, ocp_ and ocn_ connected together, v pp_ = +100v, v nn_ = -100v max4811 75 pf off-output leakage current i lk v nn_ = -100v, v pp_ = 100v, en_ = 0, out = -100v to +100v -1 +1 ? i oc n _ = - 100m a, d c - coup l ed , v c c _ = + 12v ? 5% , v e e _ = - v c c _ 22 50 low-side signal-clamp output impedance r cls i ocn_ = -100ma, dc-coupled, v cc_ = +5v ?%, v ee_ = -v cc_ 24 65 i oc p _ = - 100m a, d c - coup l ed , v c c _ = + 12v ? 5% , v e e _ = - v c c _ 28 50 high-side signal-clamp output impedance r chs i ocp_ = -100ma, dc-coupled, v cc_ = +5v ?%, v ee_ = -v cc_ 38 65 v cc_ = +12v ?%, v ee_ = -v cc_ , i cgn = 10ma, en_ = 0 100 low-side gate short impedance r lsh v cc_ = +12v ?%, v ee_ = -v cc_ , i cgn = 10ma, en_ = v dd 57.510k v cc_ = +12v ?%, v ee_ = -v cc_ , i cgn = 10ma, en_ = 0 100 high-side gate short impedance r hsh v cc_ = +12v ?%, v ee_ = -v cc_ , i cgn = 10ma, en_ = v dd 57.510k thermal shutdown thermal shutdown t shdn junction temperature rising 150 ? thermal-shutdown hysteresis 20 ? dynamic characteristics (r l = 100 , c l = 100pf, unless otherwise noted) logic input to output rise propagation delay t plh v cc_ = +12v, v pp_ = +5v, v nn_ = -5v, figure 4 15 ns logic input to output fall propagation delay t phl v cc_ = +12v, v pp_ = +5v, v nn_ = -5v, figure 4 15 ns logic input to output rise propagation delay t poh v cc_ = +12v, v pp_ = +5v, v nn_ = -5v, figure 4 15 ns logic input to output fall propagation delay t pol v cc_ = +12v, v pp_ = +5v, v nn_ = -5v, figure 4 15 ns logic input to output-rise propagation delay clamp t plo v cc_ = +12v, v pp_ = +5v, v nn_ = -5v, figure 4 15 ns
max4810/max4811/max4812 dual, unipolar/bipolar, high-voltage digital pulsers _______________________________________________________________________________________ 5 electrical characteristics (continued) (v dd = +2.7v to +6v, v cc_ = +4.75v to +12.6v, v ee_ = -12.6v to -4.75v, v nn_ = -200v to 0, v pp_ = 0 to (v nn_ + 200v), v ss the lower of v nn1 or v nn2 , t a = t j = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 3) (see figures 8, 9, and 10.) parameter symbol conditions min typ max units logic input to output-fall propagation delay clamp t pho v cc_ = +12v, v pp_ = +5v, v nn_ = -5v, figure 4 15 ns out_ rise time (gnd to v pp_ ) t r0p v p p _ = + 100v , v n n _ = - 100v , v c c _ = + 12v ? 5%, v e e _ = - v c c _ , fi g ur e 4 920ns out_ rise time (v nn_ to gnd) t rn0 v p p _ = + 100v , v n n _ = - 100v , v c c _ = + 12v ? 5%, v e e _ = - v c c _ , fi g ur e 4 17 35 ns out_ rise time (v nn_ to v pp_ ) t rnp v p p _ = + 100v , v n n _ = - 100v , v c c _ = + 12v ? 5%, v e e _ = - v c c _ , fi g ur e 4 10.5 35 ns out_ fall time (gnd to v nn_ ) t f0n v p p _ = + 100v , v n n _ = - 100v , v c c _ = + 12v ? 5%, v e e _ = - v c c _ , fi g ur e 4 920ns out_ fall time (v pp_ to gnd) t fp0 v p p _ = + 100v , v n n _ = - 100v , v c c _ = + 12v ? 5%, v e e _ = - v c c _ , fi g ur e 4 17 35 ns out_ fall time (v pp_ to v nn_ ) t fpn v p p _ = + 100v , v n n _ = - 100v , v c c _ = + 12v ? 5%, v e e _ = - v c c _ , fi g ur e 4 10.5 35 ns v cc_ = +12v ?5%, v ee_ = -v cc_ 100 out enable time from en (figure 5) t en v cc_ = +5v ?5%, v ee_ = -v cc_ 150 ns v cc_ = +12v ?5%, v ee_ = -v cc_ 100 out disable time from en (figure 5) t di v cc_ = +5v ?5%, v ee_ = -v cc_ 150 ns v cc_ = +12v ?5%, v ee_ = -v cc_ 150 clamp enable time from inc (figure 6) t en-cl v cc_ = +5v ?5%, v ee_ = -v cc_ 180 ns v cc_ = +12v ?5%, v ee_ = -v cc_ 150 clamp disable time from inc (figure 6) t di-cl v cc_ = +5v ?5%, v ee_ = -v cc_ 150 ns v pp_ = 12v, v nn_ = 0, v cc_ = +12v ?5%, v ee_ = -v cc_ 1000 short enable time from en (figure 7) t en_sh v pp_ = 5v, v nn_ = 0, v cc_ = +5v ?5%, v ee_ = -v cc_ 1000 ns v pp_ = 12v, v nn_ = 0, v cc_ = +12v ?5%, v ee_ = -v cc_ 250 short disable time from en (figure 7) t di_sh v pp_ = 5v, v nn_ = 0, v cc_ = +5v ?5%, v ee_ = -v cc_ 250 ns in p _ to in n _ over l ap tol er ance |3| ns crosstalk v pp_ = v cc_ = +5v, v nn_ = v ee_ = -5v, f = 5mhz 69 db 2nd harmonic distortion 2hd v pp_ = v nn_ = 100v, f out = 5mhz, v cc_ = 12v -48 db rms output jitter t j v cc_ = 12v 9 ps note 3: specifications are guaranteed for the stated global conditions, unless otherwise noted and are 100% production tested at t a = +25? and t a = +70?. specifications at t a = 0? are guaranteed by design. note 4: 100% production tested at t a = +25?. specifications over temperature are guaranteed by design.
max4810/max4811/max4812 dual, unipolar/bipolar, high-voltage digital pulsers 6 _______________________________________________________________________________________ typical operating characteristics (v dd = +3.3v, v cc _ = +12v, v ee _ = -12v, v ss = -100v, v pp _ = +100v, v nn _ = -100v, f out = 5mhz, t a = +25?, unless otherwise noted.) 0.30 0.36 0.34 0.32 0.40 0.38 0.48 0.46 0.44 0.42 0.50 13579111315 i cc vs. output frequency max4810/11/12 toc01 frequency (mhz) i cc (ma) 4 pulses, prf = 10khz 0 10 5 25 20 15 35 30 40 145 23 678910 i cc vs. output frequency max4810/11/12 toc02 frequency (mhz) i cc (ma) continuous switching, v pp_ = v cc_ = +5v, v nn_ = v ee_ = -5v, v dd = +3.3v, no load 0.30 0.36 0.34 0.32 0.40 0.38 0.48 0.46 0.44 0.42 0.50 0 10203040506070 i cc vs. temperature max4810/11/12 toc03 temperature ( c) i cc ( a) 4 pulses at 10mhz, prf = 10khz 5 7 6 9 8 11 10 12 02030 10 40 50 60 70 i cc vs. temperature max4810/11/12 toc04 temperature ( c) i cc (ma) continuous switching, f out = 2.5mhz, v pp_ = v cc_ = +5v, v nn_ = v ee_ = -5v, v dd = +3.3v, no load 0.40 0.52 0.48 0.44 0.60 0.56 0.76 0.72 0.68 0.64 0.80 1 3 5 7 9 11 13 15 i pp vs. output frequency max4810/11/12 toc05 frequency (mhz) i pp (ma) 4 pulses, prf = 10khz 0 20 18 16 14 12 10 8 6 4 2 22 13 2 45678910 i pp vs. output frequency max4810/11/12 toc06 frequency (mhz) i pp (ma) continuous switching, v pp_ = v cc_ = +5v, v nn_ = v ee_ = -5v, v dd = +3.3v, no load 0.40 0.52 0.48 0.44 0.60 0.56 0.76 0.72 0.68 0.64 0.80 0 10203040506070 i pp vs. temperature max4810/11/12 toc07 temperature ( c) i pp (ma) 4 pulses at 10mhz, prf = 10khz 0 3 2 1 5 4 9 8 7 6 10 0 10203040506070 i pp vs. temperature max4810/11/12 toc08 temperature ( c) i pp (ma) continuous switching, f out = 2.5mhz, v pp_ = v cc_ = +5v, v nn_ = v ee_ = -5v, v dd = +3.3v, no load 0.40 0.52 0.48 0.44 0.60 0.56 0.76 0.72 0.68 0.64 0.80 13579111315 i nn vs. output frequency max4810/11/12 toc09 frequency (mhz) i nn (ma) 4 pulses, prf = 10khz
max4810/max4811/max4812 dual, unipolar/bipolar, high-voltage digital pulsers _______________________________________________________________________________________ 7 typical operating characteristics (continued) (v dd = +3.3v, v cc _ = +12v, v ee _ = -12v, v ss = -100v, v pp _ = +100v, v nn _ = -100v, f out = 5mhz, t a = +25?, unless otherwise noted.) 0 20 18 16 14 12 10 8 6 4 2 22 13 2 45678910 i nn vs. output frequency max4810/11/12 toc10 frequency (mhz) i nn (ma) continuous switching, v pp_ = v cc_ = +5v, v nn_ = v ee_ = -5v, v dd = +3.3v, no load 0.40 0.52 0.48 0.44 0.60 0.56 0.76 0.72 0.68 0.64 0.80 0 10203040506070 i nn vs. temperature max4810/11/12 toc11 temperature ( c) i nn (ma) 4 pulses at 10mhz, prf = 10khz 0 3 2 1 5 4 9 8 7 6 10 0 10203040506070 i nn vs. temperature max4810/11/12 toc12 temperature ( c) i nn (ma) continuous switching, f out = 2.5mhz, v pp_ = v cc_ = +5v, v nn_ = v ee_ = -5v, v dd = +3.3v, no load 0 20 18 16 14 12 10 8 6 4 2 22 out rise time (gnd to v pp_ ) vs. v cc_ /v ee_ supply voltage max4810/11/12 toc13 t rop (ns) v cc_ /v ee_ supply voltage (v) +4.75/-4.75 +7.5/-7.5 +12/-12 +5/-5 +10/-10 +12.6/-12.6 r l = 100 , c l = 100pf 0 20 18 16 14 12 10 8 6 4 2 22 out fall time (gnd to v nn_ ) vs. v cc_ /v ee_ supply voltage max4810/11/12 toc14 t fon (ns) v cc_ /v ee_ supply voltage (v) +4.75/-4.75 +7.5/-7.5 +12/-12 +5/-5 +10/-10 +12.6/-12.6 r l = 100 , c l = 100pf 10 12 11 13 14 15 16 17 18 19 20 21 22 inp-to-out rise propagation delay vs. v cc_ /v ee_ supply voltage max4810/11/12 toc15 v cc_ /v ee_ supply voltage (v) t plh (ns) +4.75/-4.75 +7.5/-7.5 +12/-12 +5/-5 +10/-10 +12.6/-12.6 r l = 100 , c l = 100pf 0 6 4 2 10 8 18 16 14 12 20 0 10203040506070 inp-to-out rise propagation delay vs. temperature max4810/11/12 toc16 temperature ( c) t plh (ns) r l = 100 , c l = 100pf 10 12 11 13 14 15 16 17 18 19 20 21 22 inp-to-out fall propagation delay vs. v cc_ /v ee_ supply voltage max4810/11/12 toc17 v cc_ /v ee_ supply voltage (v) t phl (ns) +4.75/-4.75 +7.5/-7.5 +12/-12 +5/-5 +10/-10 +12.6/-12.6 r l = 100 , c l = 100pf 0 6 4 2 10 8 18 16 14 12 20 0 10203040506070 inp-to-out fall propagation delay vs. temperature max4810/11/12 toc18 temperature ( c) t phl (ns) r l = 100 , c l = 100pf
max4810/max4811/max4812 dual, unipolar/bipolar, high-voltage digital pulsers 8 _______________________________________________________________________________________ pin description pin name function 1 c gp1 channel 1 high-side gate input. connect a 1nf to 10nf capacitor between c dp1 and c gp1 as close as possible to the device. 2 , 3 v pp1 channel 1 high-side positive supply voltage input. bypass v pp1 to gnd with a 0.1? as close as possible to the device. see the power supplies and bypassing section. depending on the output, additional bypassing may be required. 4, 10, 33, 39 n.c. no connection. not connected internally. 5 op1 channel 1 high-side drain output 6 ocp1 channel 1 high-side clamp output 7, 15, 28, 36, 44, 55 gnd ground 8 ocn1 channel 1 low-side clamp output 9 on1 channel 1 low-side drain output 11, 12 v nn1 channel 1 high-side negative supply voltage input. bypass v nn1 to gnd with a 0.1? as close as possible to the device. see the power supplies and bypassing section. depending on the output, additional bypassing may be required. 13 c gn1 channel 1 low-side gate input. connect a 1nf to 10nf capacitor between c dn1 and c gn1 as close as possible to the device. 14 c dn1 channel 1 low-side driver output. connect a 1nf to 10nf capacitor between c dn1 and c gn1 as close as possible to the device. 16, 54 v cc1 channel 1 gate-drive supply voltage input. bypass v cc1 to gnd with a 0.1? as close as possible to the device. see the power supplies and bypassing section. depending on the output, additional bypassing may be required. 17 inn1 channel 1 low-side logic input (table 1) 18 inc1 channel 1 clamp logic input. clamps ocp1 and ocn1 are turned on when inc1 is high and when inp1 and inn1 are low (see table 1). 19 inp1 channel 1 high-side logic input (table 1) 20 en1 channel 1 enable logic input. drive en1 high to enable op1 and on1. pull en1 low to turn on the gate- source short circuit (see table 1). 21 shdn shutdown logic input (table 1) 22 agnd analog ground. must be connected to common gnd. 23 en2 channel 2 enable logic input. drive en2 high to enable op2 and on2. pull en2 low to turn on the gate- source short circuit. see table 1. 24 inp2 channel 2 high-side logic input (table 1) 25 inc2 channel 2 clamp logic input. clamps ocp2 and ocn2 are turned on when inc2 is high and when inp2 and inn2 are low. see table 1. 26 inn2 channel 2 low-side logic input (table 1) 27, 45 v cc2 channel 2 gate-drive supply voltage input. bypass v cc2 to gnd with a 0.1? as close as possible to the device. see the power supplies and bypassing section. depending on the output, additional bypassing may be required. 29 c dn2 channel 2 low-side driver output. connect a 1nf to 10nf capacitor between c dn2 and c gn2 as close as possible to the device. 30 c gn2 channel 2 low-side gate input. connect a 1nf to 10nf capacitor between c dn2 and c gn2 as close as possible to the device.
max4810/max4811/max4812 dual, unipolar/bipolar, high-voltage digital pulsers _______________________________________________________________________________________ 9 detailed description the max4810/max4811/max4812 are dual high-volt- age, high-speed pulsers that can be independently configured for either unipolar or bipolar pulse outputs. these devices have independent logic inputs for full pulse control and independent active clamps. the clamp input, inc_, can be set high to activate the clamp automatically when the device is not pulsing to the positive or negative high-voltage supplies. logic inputs (inp_, inn_, inc_, en_, shdn ) the max4810/max4811/max4812 have a total of nine logic input signals. shdn controls power-up and power- down of the device. there are two sets of inp_, inn_, inc_, and en_ signals: one for each channel. inp_ pin name function 31, 32 v nn2 channel 2 high-side negative supply voltage input. bypass v nn2 to gnd with a 0.1? as close as possible to the device. see the power supplies and bypassing section. depending on the output, additional bypassing may be required. 34 on2 channel 2 low-side drain output 35 ocn2 channel 2 low-side clamp output 37 ocp2 channel 2 high-side clamp output 38 op2 channel 2 high-side drain output 40, 41 v pp2 channel 2 high-side supply voltage input. bypass v pp2 to gnd with a 0.1? as close as possible to the device. see the power supplies and bypassing section. depending on the output, additional bypassing may be required. 42 c gp2 channel 2 high-side gate input. connect a 1nf to 10nf capacitor between c dp2 and c gp2 as close as possible to the device. 43 c dp2 channel 2 high-side driver output. connect a 1nf to 10nf capacitor between c dp2 and c gp2 as close as possible to the device. 46 c gc2 channel 2 high-side clamp gate input. connect a 1nf to 10nf capacitor between c dc2 and c gc2 as close as possible to the device. 47 c dc2 channel 2 high-side clamp driver output. connect a 1nf to 10nf capacitor between c dc2 and c gc2 as close as possible to the device. 48 v ee2 channel 2 negative supply input. |v ee2 | v cc2 . gate drive supply voltage for the ocp clamp. bypass v ee2 to gnd with a 0.1? as close as possible to the device. see the power supplies and bypassing section. depending on the output, additional bypassing may be required. 49 v dd logic supply voltage input. bypass v dd to gnd with a 0.1? as close as possible to the device. see the power supplies and bypassing section. depending on the output, additional bypassing may be required. 50 v ss substrate voltage. connect v ss to a voltage equal to or more negative than the more negative of v nn1 or v nn2 . 51 v ee1 channel 1 negative supply input. |v ee1 | v cc1 . gate drive supply voltage for the ocp clamp. bypass v ee1 to gnd with a 0.1? as close as possible to the device. see the power supplies and bypassing section. depending on the output, additional bypassing may be required. 52 c dc1 channel 1 high-side clamp driver output. connect a 1nf to 10nf capacitor between c dc1 and c gc1 as close as possible to the device. 53 c gc1 channel 1 high-side clamp gate input. connect a 1nf to 10nf capacitor between c dc1 and c gc1 as close as possible to the device. 56 c dp1 channel 1 high-side driver output. connect a 1nf to 10nf capacitor between c dp1 and c gp1 as close as possible to the device. ?p exposed pad. ep must be connected to v ss . do not use ep as the only v ss connection for the device. pin description (continued)
max4810/max4811/max4812 dual, unipolar/bipolar, high-voltage digital pulsers 10 ______________________________________________________________________________________ controls the on and off states of the high side fet, inn_ controls the on and off states of the low side fet, inc_ controls the active clamp and en_ controls the gate to source short. these signals give complete control of the output stage of each driver (see table 1 for all logic combinations). the max4810/max4811/max4812 logic inputs are cmos logic compatible and the logic level are refer- enced to v dd for maximum flexibility. the low 5pf (typ) input capacitance of the logic inputs reduces loading and increases switching speed. high-voltage output protection (max4811 only) the high-voltage outputs of the max4811 feature an integrated overvoltage protection circuit that allows the user to implement multilevel pulsing by connecting the outputs of multiple pulser channels in parallel. internal diodes in series with the on_ and op_ outputs prevent the body diode of the high-side and low-side fets from switching on when a voltage greater than v nn_ or v pp_ is present on the output. see figure 2. active clamps the max4810/max4811/max4812 feature an active clamp circuit to improve pulse quality and reduce 2nd harmonic output. the clamp circuit consists of an n- channel (dc-coupled) and a p-channel (ac and dc delay coupled) high-voltage fets that are switched on or off by the logic clamp input (inc_). the max4810/ max4811 feature protected clamp devices, allowing the clamp circuit to be used in bipolar pulsing circuits (see figures 1 and 2). a diode in series with the ocn_ output prevents the body diode of the low-side fet from turning on when a voltage lower than gnd is pre- sent. another diode in series with the ocp_ output pre- vents the body diode of the high-side fet from turning on when a voltage higher than ground is present. the max4812 does not have diode protection on the clamp outputs. thus, the device is suitable for use in circuits where only unipolar pulsing is required. the user can connect the active clamp input (inc_) to a logic-high voltage and drive only the inp_ and inn_ inputs to minimize the number of signals used to drive the x = don? care. 0 = logic-low. 1 = logic-high. inputs outputs sdhn en_ inp_ inn_ inc_ op_ on_ ocp_, ocn_ state 0xx x 0 high impedance high impedance high impedance powered down, inp_/inn_ disabled, gate-source short disabled 0xx x 1 high impedance high impedance gnd powered down, inp_/inn_ disabled, gate-source short disabled 10x x 0 high impedance high impedance high impedance powered up, inp_/inn_ disabled, gate-source short enabled 10x x 1 high impedance high impedance gnd powered up, inp_/inn_ disabled, gate-source short enabled 1 1000 high impedance high impedance high impedance powered up, all inputs enabled, gate-source short disabled 1 1001 high impedance high impedance gnd powered up, all inputs enabled, gate-source short disabled 1 101x high impedance v nn_ high impedance powered up, all inputs enabled, gate-source short disabled 1 110x v pp_ high impedance high impedance powered up, all inputs enabled, gate-source short disabled 1 111x v pp_ v nn_ high impedance not allowed (3ns maximum overlap) table 1. truth table
max4810/max4811/max4812 dual, unipolar/bipolar, high-voltage digital pulsers ______________________________________________________________________________________ 11 device. in this case, whenever both the inp_ and inn_ inputs are low and the inc_ input is high, the active clamp circuit pulls the output to gnd through the ocp_ and ocn_ outputs (see table 1 for more information). power-supply ramping and gate-source short circuit the max4810/max4811/max4812 include a gate- source short circuit that is controlled by the enable input (en_). when shdn is high and en is low, a 60 switch shorts together the gate and source of the high-side out- put fet. at the same time, a similar switch shorts the gate and source of the low-side output fet (table 1). the gate-source short circuit prevents accidental turn- on of the output fets due to the ramping voltage on v pp_ and v nn_ , and allows for faster ramping rates and smaller delay times between pulsing modes. shutdown mode shdn is common to both channel 1 and channel 2 and powers up or down the device. drive shdn low to power down all internal circuits (except the clamp circuits). when shdn is low, the device is in the lowest power state (1?) and the gate-source short circuit is disabled. the device takes 1? (typ) to become active when shdn is disabled. thermal protection a thermal shutdown circuit with a typical threshold of +150? prevents damage due to excessive power dis- sipation. when the junction temperature exceeds t j = +150?, all outputs are disabled. normal operation typ- ically resumes after the ic? junction temperature drops below +130?. applications information ac-coupling capacitor selection the value of all ac-coupling capacitors (between c dp_ and c gp , and between c dn_ and c gn_ ) should be between 1nf to 10nf. the voltage rating of the capaci- tor should be at least as high as v pp_ . the capacitors should be placed as close as possible to the device. because inp_ and part of inc_ are ac-coupled to the output devices, they cannot be driven high indefinitely when the device is active. power dissipation the power dissipation of the max4810/max4811/ max4812 consists of three major components caused by the current consumption from v cc_ ,v pp_ , and v nn_ . the sum of these components (p vcc_ , p vpp_ and p vnn_ ) must be kept below the maximum power-dissi- pation limit. see the typical operating characteristics section for more information on typical supply currents versus switching frequencies. the device consumes most of the supply current from v cc_ supply to charge and discharge internal nodes such as the gate capacitance of the high-side fet (c p ) and the low-side fet (c n ). neglecting the small quies- cent supply current and a small amount of current used to charge and discharge the capacitances at the inter- nal gate clamp fets, the power consumption can be estimated as follows: where f inn and f inp are the switching frequency of the inputs inn, inp respectively, and where brf is the burst repitition frequency and btd is the burst time duration. the typical value of the gate capacitances of the power fet are c n = 0.2nf, c p = 0.4nf. for an output load that has a resistance of r l and capacitance of c l , the max4810/max4811/max4812 power dissipation can be estimated as follows (assume square wave output and neglect the resistance of the switches): where c o is the output capacitance of the device. power supplies and bypassing the max4810/max4811/max4812 operate from inde- pendent supply voltage sets (only v dd and v ss are common to both channels). the logic input circuit oper- ates from a +2.7v to +6v single supply (v dd ). the level-shift driver dual supplies, v cc_ /v ee_ operate from ?.75v to ?2.6v. the v pp_ /v nn_ high-side and low-side supplies are dri- ven from a single positive supply up to +220v, from a single negative supply up to -200v, or from ?10v dual supplies. either v pp_ or v nn_ can be set at 0. bypass each supply input to ground with a 0.1? capacitor as close as possible to the device. depending on the load of the input, additional bypass- ing may be needed to keep the output of v nn_ and v pp_ stable during output transitions. for example, with p vpp =+ () ? () ? ? ? ? ? ? + cc f v v v r olin pp nn pp l __ _ 2 2 ? ? ? ? ? ? ? ? () ? ? ? ? ? ? ? ? ? ? 1 2 brf btd p vcc = () + () ? ? ? ? ? ? cv f cv f br ncc in pcc in __ 22 f fbtd ff f in inn inp () =+
max4810/max4811/max4812 dual, unipolar/bipolar, high-voltage digital pulsers 12 ______________________________________________________________________________________ c out = 100pf and r out = 100 load, additional 10? (typ) capacitor is recommended. v ss is the substrate voltage and must be connected to a voltage equal to or more negative than the more negative voltage of v nn1 or v nn2 . exposed pad and layout concerns the max4810/max4811/max4812 provide an exposed pad (ep) underneath the tqfn package for improved thermal performance. ep is internally connected to v ss . connect ep to v ss externally and do not run traces under the package to avoid possible short circuits. to aid heat dissipation, connect ep to a similarly sized pad on the component side of the pcb. this pad should be connected through to the solder-side copper by several plated holes to a large heat spreading copper area to conduct heat away from the device. the max4810/max4811/max4812 high-speed pulsers require low-inductance bypass capacitors to their sup- ply inputs. high-speed pcb trace design practices are recommended. pay particular attention to minimize level shifter v dd v cc_ c dp_ inp_ v pp_ c gp_ op_ v ss level shifter v dd v cc_ v ss ocn_ gnd level shifter v dd v cc_ c dn_ inn_ v ss on_ v nn_ c gn_ v ss short circuit level shifter v dd v ee_ c dc_ c gc_ inc_ en_ gnd _ ocp_ v ss max4810 shdn c gc_ gnd c dc_ v ee_ c dn_ c gn_ v dd v cc_ c dp_ c gp_ figure 1. max4810 simplified functional diagram for one channel
trace lengths and use sufficient trace width to reduce inductance. use of surface-mount components is recommended. supply sequencing v ss must be lower than or equal to the more negative voltage of v nn1 or v nn2 at all times. no other power- supply sequencing is required for the max4810/ max4811/max4812. typical application circuits figures 8, 9, and 10 show typical applications for the max4810/max4811/max4812. figure 8 shows the max4810 used in a bipolar pulsing connection. figure 9 shows the max4811 in a five-level pulsing applica- tion, and figure 10 shows the max4812 used in a unipolar application. max4810/max4811/max4812 dual, unipolar/bipolar, high-voltage digital pulsers ______________________________________________________________________________________ 13 level shifter v dd v cc_ c dp_ inp_ v pp_ c gp_ op_ v ss level shifter v dd v cc_ v ss ocn_ gnd level shifter v dd v cc_ c dn_ inn_ v ss on_ v nn_ c gn_ v ss short circuit level shifter v dd v ee_ c dc_ c gc_ inc_ en_ gnd _ ocp_ v ss max4811 shdn c gc_ gnd c dc_ v ee_ c dn_ c gn_ v dd v cc_ c dp_ c gp_ figure 2. max4811 simplified functional diagram for one channel
max4810/max4811/max4812 dual, unipolar/bipolar, high-voltage digital pulsers 14 ______________________________________________________________________________________ level shifter v dd v cc_ c dp_ inp_ v pp_ c gp_ op_ v ss level shifter v dd v cc_ v ss ocn_ gnd level shifter v dd v cc_ c dn_ inn_ v ss on_ v nn_ c gn_ v ss short circuit level shifter v dd v ee_ c dc_ c gc_ inc_ en_ gnd _ ocp_ v ss max4812 shdn c gc_ gnd c dc_ v ee_ c dn_ c gn_ v dd v cc_ c dp_ c gp_ figure 3. max4812 simplified functional diagram for one channel
max4810/max4811/max4812 dual, unipolar/bipolar, high-voltage digital pulsers ______________________________________________________________________________________ 15 50% 10% 90% 10% 90% 10% 90% 10% 10% 10% 50% 50% 50% 50% 50% 50% 90% 90% 50% t poh t rnp t pho t fpo t rop t fon t rno t plo t pol t phl t plh t fpn out_ inp_ inn_ inc_ = high gnd gnd v dd v pp_ v nn _ figure 4. detailed timing (r l = 100 , c l = 100pf) gnd en inc_ = high out_ (inn_ = high) out_ (inp_ = high) t en t di 50% 50% 10% 10% figure 5. enable timing (r l = 100 , c l = 100pf)
max4810/max4811/max4812 dual, unipolar/bipolar, high-voltage digital pulsers 16 ______________________________________________________________________________________ 50% en 10% 10% 10% 90% +12v -12v gnd gnd cgn_ cgp_ 1k pullup resistor between cgn_ and +12v. 1k pulldown resistor between cgp_ and -12v. t di-sh t en-sh figure 7. short-circuit timing out_ (v pp_ ) gnd out_ (v nn_ ) inc_ 10% 10% 10% t en-cl t di-cl 1k pullup resistor to v pp_ 1k pulldown resistor to v nn_ figure 6. active clamp timing
max4810/max4811/max4812 dual, unipolar/bipolar, high-voltage digital pulsers ______________________________________________________________________________________ 17 max4810 29 31 30 32 33 34 35 36 37 38 39 40 41 42 6 5 4 3 2 1 12 11 14 13 10 9 8 7 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 v nn1 c gn1 c dn1 v nn1 n.c. on1 ocn1 gnd ocp1 op1 n.c. v pp1 v pp1 c gp1 v nn2 c gn2 c dn2 v nn2 n.c. on2 ocn2 gnd ocp2 op2 n.c. v pp2 v pp2 c gp2 gnd v cc2 inn2 inc2 inp2 en2 agnd en1 inp1 inc1 inn1 v cc1 gnd shdn c dp2 gnd v cc2 c gc2 c dc2 v ee2 v dd v ss v ee1 c dc1 c gc1 v cc1 gnd c dp1 out1 -100v +100v out2 -100v +100v +12v +12v v dd v dd +12v -12v -100v +12v -12v +3v figure 8. max4810: dual bipolar pulsing, ?00v, gnd
max4810/max4811/max4812 dual, unipolar/bipolar, high-voltage digital pulsers 18 ______________________________________________________________________________________ max4811 29 31 30 32 33 34 35 36 37 38 39 40 41 42 6 5 4 3 2 1 12 11 14 13 10 9 8 7 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 v nn1 c gn1 c dn1 v nn1 n.c. on1 ocn1 gnd ocp1 op1 n.c. v pp1 v pp1 c gp1 v nn2 c gn2 c dn2 v nn2 n.c. on2 ocn2 gnd ocp2 op2 n.c. v pp2 v pp2 c gp2 gnd v cc2 inn2 inc2 inp2 en2 agnd en1 inp1 inc1 inn1 v cc1 gnd shdn c dp2 gnd v cc2 c gc2 c dc2 v ee2 v dd v ss v ee1 c dc1 c gc1 v cc1 gnd c dp1 out1 -100v +100v out1 -100v +100v +12v +12v +12v -12v -100v +12v -12v +3v figure 9. max4811: five-level pulsing, ?00v, ?0v, gnd
max4810/max4811/max4812 dual, unipolar/bipolar, high-voltage digital pulsers ______________________________________________________________________________________ 19 max4812 29 31 30 32 33 34 35 36 37 38 39 40 41 42 6 5 4 3 2 1 12 11 14 13 10 9 8 7 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 v nn1 c gn1 c dn1 v nn1 n.c. on1 ocn1 gnd ocp1 op1 n.c. v pp1 v pp1 c gp1 v nn2 c gn2 c dn2 v nn2 n.c. on2 ocn2 gnd ocp2 op2 n.c. v pp2 v pp2 c gp2 gnd v cc2 inn2 inc2 inp2 en2 agnd en1 inp1 inc1 inn1 v cc1 gnd shdn c dp2 gnd v cc2 c gc2 c dc2 v ee2 v dd v ss v ee1 c dc1 c gc1 v cc1 gnd c dp1 out1 out2 c pp c ac +100v c ac c pp +100v +12v +12v +12v +12v +3v figure 10. max4812: dual unipolar pulsing, +100v, gnd
package type package code document no. 56 tqfn t5677-1 21-0144 package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . max4810/max4811/max4812 dual, unipolar/bipolar, high-voltage digital pulsers maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2008 maxim integrated products is a registered trademark of maxim integrated products, inc.

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